1. Technical Field
The disclosure relates generally to integrated circuit (IC) fabrication, and more particularly, to forming of high dielectric constant (high-k) and metal gate stacks using a capping layer.
2. Background Art
In the integrated circuit (IC) fabrication industry, metal gate electrodes are being pursued for, for example, the 45 nanometer (nm) and 32 nm technology nodes as a replacement for doped polysilicon (poly-Si) gate electrodes for a number of reasons. Metal gate electrodes include a high dielectric constant (high-k) dielectric within a metal gate stack. The best known self aligned process flows for complementary metal oxide semiconductor (CMOS) fabrication with the high-k dielectrics and metal gate stack use a dual field effect transistor (FET) threshold voltage (Vt) work function tuning layers scheme to tune the threshold voltage of adjacent n-type metal oxide semiconductor (NMOS) region (for NFETs) and p-type metal oxide semiconductor (PMOS) region (for PFETs). That is, dual metal/dual dielectric gate stacks. One challenge for this technology is that the continual reduction in device dimensions that define, for example, the 45 nm and 32 nm technology nodes, impose an ever reducing distance between the different active regions, e.g., approximately 102 nm for the 45 nm node and approximately 72 nm for the 32 nm node. The reduction in device dimensions presents a problem because tuning layers for NMOS and PMOS regions are not interchangeable. As a result, in order to accommodate formation of the appropriate gate stack for each region, gate stack layers particular to each region must be formed in both regions and then the opposing NMOS and PMOS region's stack must be completely removed, which is costly and induces process variations. Since the distance between active regions is so small, etching the gate stacks and continuing to meet ground rule restrictions is currently unachievable for the 45 nm and 32 nm CMOS technology nodes, and beyond. In particular, the ability to form material layers such that they are thin enough to fill a gap between partially formed gate stacks and such that the materials can be removed from the gap to ultimately form the gate stacks in the NMOS and PMOS regions is currently unfeasible. Butted junctions are also not available using current practices because of the removal of layers between the different NMOS and PMOS gate stacks.